1. Field of the Invention
The invention relates to a delay control circuit, more particularly to a delay control circuit for synchronizing the phase of an input data signal with a reference clock signal.
2. Description of the Prior Art
FIG. 15 shows a display system for displaying an indication, such as a channel indication, on a monitor 400 simultaneously with a television picture. The display system of FIG. 15 includes a television signal input terminal 104 for receiving a television signal, a television tuner 200 for converting a television signal to a picture signal, a data signal input terminal 102 for receiving a data signal, such as channel number superimposed on the monitor 400, a delay control circuit 100 for image-processing the data signal input to the input terminal 102, a reference clock input terminal 101 for receiving a reference clock to be supplied to the delay control circuit 100 and the television tuner 200, a line memory 300 for storing picture elements corresponding to one scanning line, a monitor 400 such as a Braun tube, a plasma display, a liquid crystal panel (TFT), or a television display 401 in the monitor 400 for displaying the television picture received from the television tuner 200 and the channel indication received from the delay control circuit 100.
In FIG. 15, the television signal input to the television signal input terminal 104 is image-processed by the television tuner 200 and transmitted to the line memory 300 for each scanning line. On the other hand, the data signal input to the data signal input terminal 102 is image-processed by the delay control circuit 100 and transmitted to the line memory 300 for each scanning line. The television signal output from the television tuner 200 and the data signal output from the delay control circuit 100 are composed by the line memory 300 and displayed on the monitor 400. The data signal is displayed at a fixed location of the monitor 400.
The reference clock signal is supplied to the television tuner 200 and the delay control circuit 100 via the reference clock input terminal 101. The television tuner 200 and the delay control circuit 100 are processed by the same reference clock signal, respectively. Each output signal from the delay control circuit 100 and the television tuner 200 is output to the line memory 300 and superimposed and displayed on the monitor 400. Therefore, if the output signal from the television tuner 200 and the output signal from the delay control circuit 100 are not synchronized, the television signal from the television tuner 200 and the data signal from the delay control circuit 100 are shifted in the line memory 300, and therefore the data signal from the delay control circuit 100 is not displayed on a desired location on the monitor 400. Accordingly, the delay control circuit 100 must precisely synchronize the data signal input from the data signal input terminal 102 with the reference clock signal.
For such a delay control circuit, for example, a circuit using the delay circuit shown in FIG. 16 is known. FIG. 16 is a block diagram showing a conventional delay control circuit for controlling delay of the input data signal against the reference clock input signal. FIG. 17 shows an example of the delay circuit 2 of FIG. 16. FIG. 18 shows an example of an output circuit 3 of FIG. 16. FIGS. 19A-19E are timing charts showing the operation of the delay control circuit shown in FIG. 16.
In FIG. 16, a terminal T of a D flip-flop 1 is supplied with the reference clock signal via the reference clock input terminal 101 (see FIG. 19A), and the terminal D of the D flip-flop 1 is supplied with a data signal (see FIG. 19B), such as a superimposed signal supplied via the data signal input terminal 102. The delay circuit 2 delays the data signal from the D flip-flop 1 by a predetermined time and outputs it to an output circuit 3. The output circuit 3 gives a predetermined delay to the data signal output from the delay circuit 2 and outputs the delayed data signal to an output terminal 103 so that it is synchronized with the reference clock signal.
The delay circuit 2 of FIG. 17 includes an input terminal 203, a plurality of inverters 4a-4d, and an output terminal 204, and has a delay corresponding to the sum of delays of these inverters. The output circuit 3 of FIG. 18 includes an input terminal 204, inverters 4c-4h, and an output terminal 103. The output circuit 3 has the delay corresponding to the sum of delays of these inverters. Further, the output circuit 3 not only provides a delay, but also operates as a buffer for an external circuit.
The operation of the conventional delay control circuit shown in FIG. 16 is described below using FIGS. 19A-19E. FIG. 19C shows that the input data signals shown in FIG. 19B, input from the outside, is latched at the falling edges of the reference clock signal shown in FIG. 19A and is synchronized with the reference clock signal. The data signal output from the D flip-flop 1 is delayed by a predetermined delay .DELTA. t1 in the delay circuit 2 as shown in FIG. 19D. Further, the output circuit 3 gives a predetermined delay .DELTA. t2 to the output terminal 103 as shown in FIG. 19E. By adjusting the sum (.DELTA. t1+.DELTA. t2) of the delay .DELTA. t1 and .DELTA. t2 to equal the period T of the reference clock signal, that is, .DELTA. t1+.DELTA. t2=T, the data signal output from the output circuit 3 can be synchronized with the falling edge of the reference clock signal.
In this way, in the conventional delay control circuit, the number of stages of the inverters 4a-4d in the delay circuit 2 and the number of the stages of the inverters 4e-4h in the output circuit 3 are set so that the sum of the delay of the circuit (.DELTA. t1+.DELTA. t2) is the same as the period T. In this way, by the cascade connection of a plurality of the inverters, the input data signal is output synchronously with the reference clock signal at a change point of the reference clock signal, with the fixed delay (inherent delay determined by the inverter).
However, in the conventional current delay control circuit, the delay depends on the number of inverters. Therefore, when there are some changes in the ambient temperature and the source voltage supplied to the delay control circuit, the delay changes according to the external conditions. In other words, if the ambient temperature or the source voltage changes, the length of the delay shifts from the period of the reference clock signal and the output data signal is not synchronized with the reference clock signal at the falling edge of the reference clock signal.
For example, when the source voltage decreased or the ambient temperature increases, the length of the delay increases in each inverter in the delay circuit 2 and the output circuit 3, so the total delay of the delay control circuit also increases. FIGS. 20A-20E are timing charts showing signals at respective points in the delay control circuit of FIG. 16 when the source voltage decreases or the ambient temperature increases. As shown in FIG. 20B, the rise and fall of the input data signals, such as a superimposed signal received from the outside, are latched at each falling edge of the reference clock signal as shown in FIG. 20A, so the output signal from the D flip-flop 1 is synchronized with the reference clock as shown in FIG. 20C. The output signal from the D flip-flop 1 is delayed in the delay circuit 2. However, if the source voltage falls or the ambient temperature rises, a delay .DELTA. t1a, which is larger than the normal delay .DELTA. t1, is generated as shown in FIG. 20D. Further, in the output circuit 3, a delay .DELTA. t2a, which is larger than the normal delay .DELTA. t2, is generated as shown in FIG. 20E. Therefore, since the predetermined delay (.DELTA. t1+.DELTA. t2) is changed to (.DELTA. t1a+.DELTA. t2a) via the delay circuit 2 and the output circuit 3, the delay (.DELTA. t1a+.DELTA. t2a) becomes larger than T (.DELTA. t1a+.DELTA. t2a&gt;T) and the output data signal from the output circuit 3 does not synchronize with the reference clock signal at the falling edges of the reference clock signal as shown in FIG. 20E. From this reason, there is a serious problem in that the input data signal is not displayed at a desired location on the monitor 400. Further, there is a disadvantage in that the superimposed picture becomes unstable since jitter occurs in the superimposed picture.